1. Field of the Invention
The present invention relates to a magnetic memory for storing information and a driving method therefor and, more particularly, to a nonvolatile memory using a ferromagnet and a driving method therefor.
2. Related Background Art
In general, a ferromagnet has a property that magnetization generated within the ferromagnet by an externally applied magnetic field remains even after removal of the external magnetic field (this is called residual magnetization). The resistance of the ferromagnet changes depending on the magnetization direction, the presence/absence of magnetization, or the like. This is called a magnetoresistance effect. The change ratio of the resistance is called a MR ratio (MagnetoResistance ratio). Materials having high MR ratios are a GMR (Giant MagnetoResistance) material and a CMR (Colossal MagnetoResistance) material. These materials consist of metals, alloys, composite oxides, and the like. Examples of these materials are transition metals and rare earth metals such as Fe, Ni, Co, Gd, and Tb, alloys of them, and composite oxides such as LaxSr1-xMnO9 and LaxCa1-xMnO9. A nonvolatile memory for storing information by selecting the resistance depending on the difference in magnetization direction or the presence/absence of magnetization by utilizing the residual magnetization of such a magnetoresistance material can be constituted. This nonvolatile memory is called an MRAM (Magnetic Random Access Memory).
Most of MRAMs which have recently been developed adopt the following method. That is, ferromagnetic memory cells for storing information by residual magnetization of the ferromagnet of a giant magnetoresistance material are formed. A change in resistance by the difference in magnetization direction is converted into a voltage to read out stored information. In addition, the magnetization direction of a ferromagnetic memory cell is changed by a magnetic field induced by flowing a current through a write wire, and information can be written in the memory cell or rewritten.
The cell structure and driving method of an MRAM are described in R. E. Scheuerlein (1998, Proc. of Int NonVolatile Memory Conf. p. 47).
This reference proposes an MRAM in which a pair of write lines and a pair of read lines are laid out to cross each other, and an MRAM (matrix type) in which a pair of crossing wires serve as both write and read lines and which is made up of memory cells each containing a giant magnetoresistive thin film and diodes series-connected to the memory cells.
These conventional MRAMs employ the following driving method. In reading out information from memory cells arrayed in a matrix, a bit line connected to a target memory cell is charged to a voltage level (to be referred to a target voltage Vt hereinafter) suitable for read operation. The target voltage Vt is applied across a variable resistor which constitutes the memory cell, thereby extracting a signal current flowing through the variable resistor.
The bias voltage (target voltage Vt) dependency of the MR ratio reported in the materials (p. 15, FIG. 8) of the 117th Symposium (2000/12/22) of the Magnetics Society of Japan reveals that the MR ratio has a high bias dependency. For a high bias voltage, the MR ratio is difficult to maintain. In read operation of the MRAM, it is important to supply a target voltage Vt of about 100 to 300 mV with high precision.
FIG. 10 is a circuit diagram for explaining read operation of a conventional MRAM. No selection switch is illustrated in FIG. 10 on the assumption that a memory cell subjected to read operation has already been selected.
Referring to FIG. 10, only a variable resistor R and a field effect type transistor Tb for supplying the target voltage Vt are illustrated. In FIG. 10, the gate terminal of the field effect type transistor Tb receives a bias voltage Vb, and a source terminal voltage, i.e., target voltage Vt (=Vbxe2x88x92Vgs) is applied in accordance with a gate-source voltage Vgs.
A signal current Isig flows through the variable resistor R in accordance with the target voltage Vt, and is transferred with a gain of 1 from the source terminal to drain terminal of the field effect type transistor Tb. More specifically, as shown in the signal current Isigxe2x80x94target voltage Vt characteristic of FIG. 11, the target voltage Vt is determined as a voltage value at an intersection point 113 between an I-V characteristic curve 111 of the variable resistor R and an I-V characteristic curve 112 of the field effect type transistor Tb.
As is apparent from the graph of FIG. 11, the target voltage Vt cannot be maintained at a predetermined voltage upon large variations in the burden of the variable resistor R connected as the load of the field effect type transistor Tb. In particular, the burden of a bit line in an indefinite state in which no connected memory cell is selected is greatly different from the burden exhibited when a memory cell is selected. Thus, the voltage level of the bit line is very different from the target voltage Vt.
FIG. 12 shows the circuit arrangement of a magnetic memory as an example of a conventional magnetic memory. FIG. 12 is a circuit diagram briefly showing a conventional magnetic memory circuit 10 having a memory array 20 in which a plurality of memory cells are arrayed at the intersections of word and sense lines.
The magnetic memory circuit 10 is constituted by the memory array 20, a decoder 40, and a comparator 60. The memory array 20 is logically divided into a first array portion 20A and second array portion 20B, which are represented by dotted frames. The decoder 40 is comprised of a lateral decoder 40A and vertical decoder 40B, which are coupled to an address bus 70. Word lines 21 to 24 and 31 to 34 are coupled to the lateral decoder 40A via a lateral switching circuit 41. Sense lines 25 to 27 and 35 to 37 are coupled to the vertical decoder 40B via a vertical switching circuit 51. The word lines 21 to 24 and 31 to 34 and the sense lines 25 to 27 and 35 to 37 have intersections within the memory array 20 where memory cells are located. For example, a memory cell 29 within the first array portion 20A is located at the intersection of the word line 21 and sense line 25. By selecting the word line 21 and sense line 25, the memory cell 29 is activated. Then, a read/write process is executed. Output lines 28 and 38 for the sense lines 25 to 27 and 35 to 37 are respectively connected to the positive and negative outputs of the comparator 60. As a conventional magnetic memory read method, information (magnetization information) recorded by magnetization by selecting an arbitrary memory cell at random is read out.
FIG. 13 is a timing chart for explaining an operation when arbitrary memory cells are selected from a conventional magnetic memory to successively read out pieces of information. FIG. 13 shows the waveform of a voltage VBL of a bit line BL, that of the signal current Isig, and that of a load RBL viewed from the bit line when pieces of information are successively read out from arbitrary memory cells.
As shown in FIG. 13, in the conventional magnetic memory read method, an arbitrary bit line BL and memory cell are selected. Then, the voltage VBL of the selected bit line BL is charged up to the target voltage Vt over a time tc (charge time), and information is then read out.
In the conventional magnetic memory, every time a memory cell from which magnetization information is to be read out is selected, the bit line connected to the memory cell must be charged up to the target voltage Vt. The time taken to charge a bit line inhibits high-speed read of magnetization information.
The present invention has been made to overcome the conventional drawbacks, and has as its object to provide a magnetic memory capable of reading out information at high speed, and a driving method therefor.
To achieve the above object, the present invention discloses the following means.
(1) According to the present invention, a magnetic memory comprises a plurality of variable resistors arrayed as memory elements in a matrix, a plurality of bit lines which each of is arranged on each row of the matrix and connected to one terminal of each of variable resistors belonging to the same row, a read circuit which detects resistance values of the variable resistors based on currents flowing through the bit lines, and at least one load element arranged on the bit lines independently of the memory elements.
The respective portions are preferably designed as follows.
Each load element includes a resistor having the same structure as a structure of the variable resistor, a resistor having a structure different from the structure of the variable resistor, a current source, a diode, or a combination of the resistor, the current source, and the diode. Each variable resistor includes a magnetoresistive element.
The magnetoresistive element is magnetized mainly perpendicular to a film surface.
The magnetoresistive element is magnetized mainly parallel to a film surface.
A magnetic memory further comprises a plurality of switches which correspond to the variable resistors and select the variable resistors.
Each switch includes a field effect type transistor, a bipolar transistor, a thin film transistor, a diode, or a combination of the field effect type transistor, the bipolar transistor, the thin film transistor, and the diode.
(2) According to the present invention, a method of driving a magnetic memory which has a plurality of variable resistors arrayed in a matrix, a plurality of switches connected to the plurality of variable resistors, and a plurality of bit lines arranged on respective rows of the matrix, one terminal of each variable resistor being connected to a corresponding bit line, and the other terminal being connected to a corresponding switch, comprises the steps of suppressing variations in voltages of the bit lines, applying a predetermined voltage to the variable resistors, and detecting information written in the variable resistors based on currents flowing through the variable resistors.
The respective steps are preferably designed as follows.
In the step of suppressing variations in the voltages of the bit lines, one of the plurality of switches connected to the same bit line is always turned on.
In the step of suppressing variations in the voltages of the bit lines, one of the plurality of variable resistors connected to the same bit line is always selected.
In the step of suppressing variations in the voltages of the bit lines, a current is flowed to load elements arranged on the respective bit lines.